This invention relates in general to the field of semiconductors, and particularly to multi-ported semiconductor register cells.
Digital circuits commonly employ registers that store data. In particular, microprocessors typically include a set of registers, commonly referred to as a register file, for storing instruction operands and results. An example of a microprocessor register file is a floating-point register file, which is an array of registers for holding operands and results of a floating-point unit. The floating-point register file can be relatively large. For example, the user-visible floating-point register file for an x86 architecture floating-point unit comprises eight 80-bit registers.
Typically, there are multiple functional blocks within a microprocessor that require access to a register file. One reason for this is that modern microprocessors are typically pipelined. That is, the processor includes multiple stages, each of which executes a portion of an instruction as it moves through the stage. Consequently, the processor is executing multiple instructions at the same time. As a result, multiple functional blocks within the various stages of the pipeline may need to read data from and write data to the register file. For example, a cache within the processor may need to write data to the register file or read data from the register file. Similarly, the arithmetic and logic units in the processor need to read and write data from and to the register file. Still further, stages that transfer data between the processor and memory require access to the register file.
Frequently, the various functional blocks within the processor need to access the register file simultaneously, i.e., during the same clock period. If the register file is designed to only allow one functional block to access the register file at a time, then the other functional blocks needing access must wait. This can be detrimental to performance since it may cause various stages in the pipeline to stall waiting for the functional block to access the register file, which defeats the advantages of the pipelined nature of the processor.
To address this problem, processors typically include multi-ported register files. A multi-ported register file includes multiple read and write ports that make the register file capable of being read from and written to by multiple functional blocks simultaneously.
For example, assume a register file has at least four write ports and two read ports. From such a register file, a data cache might write data to a first register in the register file, a first arithmetic logic unit might write an instruction result to a second register, a second arithmetic logic unit might write another instruction result to a third register, a third arithmetic logic unit might write another instruction result to a fourth register, a store stage might read an instruction result from a fifth register for writing to memory, and an address generator might read an address operand from a sixth register, all in the same clock cycle.
Multi-ported register files are made up of multi-port register cells. Each multi-port register cell stores one bit. The multi-port cells are coupled together to form a register, and the registers are arranged together into the register file. Each multi-port register cell has multiple write ports and multiple read ports. The ports include metal wires that carry data and control signals to the cell for reading and writing the cell. The data and control signals are coupled to transistors in the register cell that store the bit value or act as control logic to determine which ports will read and write the cell.
A problem with conventional multi-port register cells that are used to create multi-port register files is extreme metal wire congestion in the register file due to the large number of wires that accompany the large numbers of ports. The congestion creates routing and space problems in the register file.
In a typical cell, the size of the semiconductor layers that make up the transistors comprising the cell dictate the size of the cell. Another problem in some conventional multi-port register cells is that the large number of metal wires may dictate the size of the cell, rather than the size of the semiconductor layers. Some conventional register cells attempt to alleviate this problem and the wire congestion problem by reducing the number of metal wires, but do so by adding transistors, thereby increasing the cell size.
Therefore, what is needed is a register cell that is smaller and has a reduced number of metal wires.
The present invention provides a register cell that reduces the number of metal wires over most conventional register cells without increasing the number of transistors. Accordingly, in attainment of the aforementioned object, it is a feature of the present invention to provide a register cell. The register cell includes a storage element with true and complement inputs. The register cell also includes N write circuits. Each of the N write circuits is coupled to the storage element. Each of the N write circuits includes a first input wire that transmits a binary value to write into the storage element. Each of the N write circuits also includes a first transistor, coupling the first input wire to the true input. Each of the N write circuits also includes second and third transistors, coupled in series to the complement input. The first input wire is also coupled to the third transistor to selectively turn on the third transistor to provide a complement of the binary value to the second transistor. Each of the N write circuits also includes a second input wire, coupled to the first and second transistors, that selectively turns on the first and second transistors to selectively enable writing the binary value to the storage element.
In another aspect, it is a feature of the present invention to provide a register cell. The register cell includes a storage element with true and complement inputs. The register cell also includes N write circuits. Each of the N write circuits is coupled to the storage element. Each of the N write circuits consists essentially of first and second input wires and first, second, and third transistors. The first input wire transmits a binary value to write into the storage element. The first transistor couples the first input wire to the true input. The second and third transistors are coupled in series to the complement input. The first input wire is also coupled to the third transistor to selectively turn on the third transistor to provide a complement of the binary value to the second transistor. The second input wire is coupled to the first and second transistors and selectively turns on the first and second transistors to selectively enable writing the binary value to the storage element.
In another aspect, it is a feature of the present invention to provide a register cell. The register cell consists essentially of a storage element with true and complement inputs, N write circuits and M read circuits, each coupled to the storage element. Each of the N write circuits includes a first input wire that transmits a binary value to write into the storage element. Each of the N write circuits also includes a first transistor, coupling the first input wire to the true input. Each of the N write circuits also includes second and third transistors, coupled in series to the complement input. The first input wire is also coupled to the third transistor to selectively turn on the third transistor to provide a complement of the binary value to the second transistor. Each of the N write circuits also includes a second input wire, coupled to the first and second transistors, that selectively turns on the first and second transistors to selectively enable writing the binary value to the storage element.
In another aspect, it is a feature of the present invention to provide a register cell. The register cell includes a storage element that stores a bit. The register cell also includes N write ports. Each of the N write ports includes exactly two metal wires. The register cell also includes N write circuits. Each of the N write circuits couples a corresponding one of the N write ports to the storage element. Each of the N write circuits includes exactly three transistors.
In another aspect, it is a feature of the present invention to provide a multi-ported register cell. The multi-ported register cell includes a storage element that stores a bit. The multi-ported register cell also includes N sets of only three transistors for writing the bit into the storage element. Each of the N sets of only three transistors is coupled to the storage element. The multi-ported register cell also includes N sets of only two metal wires for writing the bit into the storage element. Each of the N sets of only two metal wires is coupled to a corresponding one of the N sets of only three transistors.
An advantage of the present invention is that it significantly reduces the number of metal wires required per write port over some conventional register cells. This has the advantageous benefit of reducing metal wire congestion in a register file comprised of many of the cells. Additionally, the present invention reduces the number of transistors, and therefore semiconductor layer space, required per write port significantly over other conventional register cells. Consequently, the register cell of the present invention is smaller than conventional register cells. The reduction in metal wire congestion and register cell size reduces the overall size of the register file, which consequently potentially reduces the overall die size of a processor including the register cell of the present invention.
Other features and advantages of the present invention will become apparent upon study of the remaining portions of the specification and drawings.